Programmable logic devices (“PLDs”) exist as a well-known type of integrated circuit (“IC”) that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (“PLAs”) and complex programmable logic devices (“CPLDs”). One type of a programmable logic device, called a field programmable gate array (“FPGA”), is very popular because of a superior combination of capacity, flexibility, time-to-market, and cost.
An FPGA typically includes an array of configurable logic blocks (“CLBs”) and programmable input/output blocks (“IOBs”). The CLBs and IOBs are interconnected by a programmable interconnect structure. The CLBs, IOBs, and interconnect structure are typically programmed by loading a stream of configuration data (“bit-stream”) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect structure are configured. CLBs and IOBs form the programmable part of an FPGA referred to as the “FPGA fabric”, which is subject to program control of the configuration memory cells. Similarly, the interconnect structure is programmable via programmable interconnect points (“PIPs”). Each IOB, CLB and PIP conventionally includes or has associated therewith a configuration memory cell. FPGAs may also contain other types of known circuitry.
Heretofore, configuration memory was not used as buffer memory.
Configuration memory controls configurable logic. By storing configuration data in a non-configuration data format, such as an encrypted or a compressed format, configuration memory heretofore could lead to creation of one or more contending electrical paths (“electrically contentious on-chip environment”). An electrically contentious on-chip environment may consume excessive amounts of power and may lead to burning up the programmable logic device.
To guard against such contention, software has been created to check a design prior to instantiation in configurable logic to ensure that no contending electrical paths will be created. Moreover, error checking of received data frames of configuration data is done by a programmable logic device to ensure that bits have not changed from their intended value, which if written to configuration memory may setup contending electrical paths. Thus, heretofore to store encrypted or compressed configuration data, even temporarily, in configuration memory could lead to a catastrophic result.
However, users of programmable logic devices may use millions or tens of millions of bits to configure a programmable logic device. Because configuration data often contains sensitive information regarding a design, it would be desirable to encrypt such configuration data before providing it to a programmable logic device for receipt in encrypted form by such programmable logic device.
Unfortunately, decryption may take too many clock-cycles and may use many available dedicated on-chip frame buffers. To limit latency, while providing on-chip decryption, dedicated decryption circuitry is conventionally formed on a programmable logic device. This dedicated decryption circuitry, while limiting clock-cycle latency, consumes a significant amount of area of the programmable logic device. Moreover, accommodating a variety of available decryption algorithms may further consume area of the programmable logic device.
Additionally, because configuration data may be relatively voluminous, it may be desirable to store it in a compressed form. This would reduce external memory used for storing configuration data. However, on-chip decompression would further consume clock cycles possibly exceeding on-chip frame buffers absent dedicated on-chip decompression circuitry.
Conventionally, configuration data is clocked into a programmable logic device, whether serially or in parallel, from external memory. Though each bit or each word is clocked into memory at a time, configuration data is provided in data frames. In implementations with a “handshake” signal, a data clock rate may be slowed to accommodate slower processing by a programmable logic device. However, in implementations where no such handshake signal is present, data clock rate (“line rate”) is not subject to control by the programmable logic device. Thus, slowing data clock rate to accommodate on-chip decryption or decompression, for example, is not available in those implementations.
Accordingly, it would be desirable to provide a programmable logic device where configuration memory may be used to buffer configuration data in an encrypted or compressed form.